Semiconductor chips are usually produced on semiconductor wafers, which are conventionally diced into single chips by sawing. Currently known dicing methods also include laser dicing and trench dicing or suitable combinations thereof. These methods are used to divide the wafer along sawing streets surrounding each chip and are part of the packaging process. In case of trench dicing a masking layer is structured by a lithographic process to define the sawing streets. The structured masking layer is then used as a mask in an etching step to produce trenches in the semiconductor wafer along the sawing streets, optionally by deep reactive ion etching (DRIE). Trench dicing has the advantage that the spaces between the chips can be much smaller compared to conventional sawing, and the productivity is higher than in laser dicing. Trench dicing allows the lateral width of the sawing streets to be reduced from typically about 60 μm to 20 μm or even smaller. The smaller the sawing street, the larger is the yield of good die per wafer. Contrary to a sawing method, trench dicing avoids the risk of small pieces breaking off from the chip edges during dicing. Therefore trench dicing is increasingly used for packaging of semiconductor chips.
WO 2011/159456 A2 discloses a semiconductor device including a light-to-heat conversion layer for a wafer support system, which can be used instead of a conventional handling wafer in the manufacturing process for three-dimensional integrated circuits.
WO 2012/143353 A1 discloses a dicing method wherein a trench is formed at a first surface of a carrier comprising electrical components. The carrier is cut through from a second surface opposite the first surface. Thus the material is prevented from breaking out of the carrier during dicing.
U.S. Pat. No. 6,420,776 B1 discloses a method of opening the scribe line at the front side, attaching a holding material such as a tape to silicon dioxide, and then forming groove-type trenches from the backside of wafer opposite the IC by a laser to a desired depth, and finally mechanically cracking the remaining silicon thickness below the scribe line to release the dies.
U.S. Pat. No. 6,573,156 B1 discloses a method for singlation of chips by etching a first trench, filling the trench with a holding material such as parylene, etching a second trench from the backside, removing the holding material by dry etching and releasing the chips.
U.S. Pat. No. 7,482,251 B1 discloses a method of singlation of dies by etching a trench from the top side of the wafer, forming underbump metallization and bumps on the top side and releasing the chips by removing the semiconductor material from the bottom side of the wafer until the trenches are opened.
U.S. Pat. No. 7,566,634 B2 discloses a further method for trench dicing of chips in wafer level packaging (WLP). The substrate is partially divided by etched trenches and afterwards thinned.
U.S. Pat. No. 8,021,923 B2 discloses a method of producing through-hole vias formed along the sawing streets by a partial sawing process to allow stacking of chips. Pads are connected to a via hole formed within organic material such as polyimide within a sawing street that has been partially etched.
U.S. Pat. No. 8,153,464 B2 discloses a method of singulating a semiconductor die from a wafer by etching trenches into the wafer, depositing a passivation layer into the trenches to form a plug on the bottom of the trenches to protect the dies and immobilize them during singulation, and forming a rigid carrier layer or plate at the first side of the wafer to secure the dies. The wafer is then ground from the back side to expose the bottom of each trench. A metal layer is formed on the back surface of the wafer. A dicing tape is added, the carrier layer is removed, and the die is separated from the wafer by laser cutting or by flexing the tape.
U.S. Pat. No. 8,198,705 B2 discloses a method to form trenches along saw streets on the backside of the wafer opposite integrated circuits covered by a glue layer and a handling wafer. The pattern is transferred by DRIE until the glue layer is reached, and the wafer is thus divided into chips.
U.S. Pat. No. 8,236,611 B1 discloses a method for die singulation using a trench etch process from the backside of a die using a first handling wafer. A second handling wafer is attached to the front side comprising integrated components.
US 2008/0153265 A1 discloses a method of die singulation by forming trenches along the sawing streets on the front side and removing the wafer from the backside until the trenches are opened and the die are released.